Curriculum
Digital Verification Training
Digital Verification Course
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Module -1 : Explanation of ASIC flow and its operations
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Module- 2: Veriog HDL coding, modelling techniques, data types
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Module- 3 : SystemVerilog introduction, scheduling regions
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Module -4: Universal Verification methodology introduction
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Module – 5: SystemVerilog Assertion introduction
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Text lesson
Digital Verification Introduction
COURSE OUTCOMES
By the end of this course, the learners will be able to
- Explanation of ASIC flow. Overall working of each and every teams in ASIC flow.
- This introduces the basics of the VHDL language for logic design. It describes the use of VHDL as a design entry method for logic design in ASICs. Many examples of combinatorial and synchronous logic circuits are presented and explained. Finally, use of simulation as a means of testing Verilog circuit designs is demonstrated.
- It offers to mastering SystemVerilog for effective hardware verification. This course the overall understanding of language concepts to advanced topics like object-oriented programming, randomization, and functional coverage. In addition it offers hands on SystemVerilog Labs to gain hands on experience in using SystemVerilog Language concepts.
- It offers to mastering UVM for robust hardware verification. From an overview of UVM to in-depth modules covering UVM TB architecture, factory, stimulus modeling, and much more to equip you with the skills needed for effective verification methodologies. Engage in UVM Labs, create testbench components.
- It offers to mastering SystemVerilog Assertions (SVA). From understanding the basics to connecting assertions to the Design Under Test (DUT), this course covers SVA introduction, building blocks, system functions, writing sequences, implication operators, repetition operators. In addition it offers practical labs to reinforce your understanding of Assertion Based Verification.