Physical verification Introduction

Course Objectives

This course delves into the complexities of physical design and verification in VLSI (Very Large Scale Integration). It aims to equip candidates with a robust foundation in the methodologies and techniques used in the physical implementation and validation of integrated circuits. The course is ideal for students aiming for careers in semiconductor design and manufacturing. 

Course Outcomes

By the end of this course, learners will be able to: 

• Understand the complete VLSI design flow and the role of physical design. 
• Perform floorplanning, placement, Clock Tree Synthesis (CTS), and routing using industry-standard tools.
• Apply timing analysis and optimization techniques to ensure design performance.
• Conduct Design Rule Checks (DRC), Layout vs. Schematic (LVS) verification, and advanced checks like ERC, PERC, Soft Check, Antenna Effect, Metal Density, and XOR.
• Implement power analysis and optimization strategies in VLSI designs.
• Perform Logic Equivalence Checking (LEC) to ensure functional consistency between different stages of design.