RTL Design and Integration Introduction

COURSE OBJECTIVES

This course is to develop the engineers expertise in all the aspects of functional verification including ASIC flow, Advanced digital design, Verillog, System Verilog ,Synthesis ,Clock Domain Crossing (CDC), AMBA protocol family. It includes theory as well as practical sessions.

COURSE OUTCOMES

By the end of this course, learners will be able to:

• Explain the ASIC flow and the overall working of each team involved in the process.
• Understand the basics of the VHDL language for logic design, including its use as a design entry method for ASICs. This includes many examples of combinatorial and synchronous logic circuits, and the use of simulation for testing Verilog circuit designs.
• Master SystemVerilog for effective hardware verification, covering language concepts and basic topics like enumeration, arrays, loops, and interfaces. Gain hands-on experience through SystemVerilog labs.
• Understand and master Clock Domain Crossing (CDC), a critical concept in RTL Design. This includes principles, techniques, and best practices for reliable data transfer, covering clock domains, synchronizers, metastability, data corruption, and solutions for CDC errors. Learn RTL CDC techniques such as synchronizer design and FIFO design
• Master the process of synthesis, learning to synthesize RTL designs into gate-level netlists. Understand logic synthesis principles and optimization techniques, and gain skills in timing analysis and optimization.